1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to improvements in connections between word lines and memory cell array blocks.
2. Description of the Prior Art
Recently, there has been considerable effort towards increasing memory capacity. As the memory capacity increases, charging and discharging of currents flowing in bit lines increases. This increases an instantaneous or peak current flowing in the memory when sense amplifiers operate. Hence, the potential of a power supply decreases and the ground potential increases. These phenomena cause erroneous detection of the logical levels of input signals and cause the device to malfunction.
In order to eliminate the above disadvantages, an improved arrangement has been proposed in which a memory cell array is divided into a plurality of blocks, and sense amplifiers and active pull-up circuits respectively related to the memory cell blocks are activated at different operation timings. With the above arrangement, it becomes possible to reduce the instantaneous current flowing in the memory when the sense amplifiers and/or the active pull-up circuits operate.
The above arrangement is proposed in Japanese Laid-Open Patent Publication No. 62-114193. FIG. 1 shows the arrangement shown in the above publication. The entire memory cell array is equally divided into four memory cell blocks MA1-MA4, which respectively include peripheral circuits, such as sense amplifiers, address decoders and input/output buffers. Each of the memory cell blocks MA1-MA4 has a memory capacity equal to 1/4 the memory capacity of the entire memory cell array. An active pull-up circuit driving system 20 supplies active pull-up operation starting signals .phi.R1, .phi.R2, .phi.R3 and .phi.R4 to the memory cell blocks MA1, MA2, MA3 and MA4, respectively. These signals .phi.R1-.phi.R4 are applied, as clock signals .phi.R, to active pull-up circuits in the memory cell blocks MA1-MA4, respectively. Hence, the active pull-up circuits in the memory cell blocks MA1-MA4 start respective active pull-up operations in response to receipt of the clock signals .phi.R1-.phi.R4.
FIG. 2 is a circuit diagram showing the periphery of a sense system in a conventional DRAM (Dynamic Random Access Memory). FIG. 3 is a waveform diagram of signals observed at nodes in the circuit configuration shown in FIG. 2. Symbols shown in FIG. 3 have the same meanings as corresponding symbols shown in FIG. 2. A signal /RAS ("/" means a low active signal and /RAS corresponds to RAS in FIG. 3).
A pair of bit lines BL and XBL are connected to data buses I/O and XI/O via transistors Q00 and Q01, which are turned ON and OFF in response to an output signal of a column decoder 10. Memory cells MC, each having one transistor and one capacitor, are alternately connected to the bit lines BL and XBL. The memory cells MC connected to the bit line XBL are called dummy memory cells DMC. Word lines WL are respectively connected to the memory cells MC connected to the bit line BL, and dummy word lines WLDM are respectively connected to the dummy memory cells DMC connected to the bit line XBL. When one of the word lines WL is selected, the capacitor of the corresponding memory cell MC is connected to the bit line BL. When one of the dummy word lines WLDM is selected, the capacitor of the corresponding dummy memory cell DMC is connected to the bit line XBL. The bit lines BL and XBL are coupled to a precharge power supply line VPR via transistors Q.sub.PR0 and Q.sub.PR1, respectively. These transistors Q.sub.PR0 and Q.sub.PR1 are concurrently turned ON and OFF in response to a precharge clock signal .phi.PR.
A sense amplifier SA and an active pull-up circuit AP are connected to the bit lines BL and XBL. The sense amplifier SA senses and amplifies the difference between the potentials of the bit lines BL and XBL. The operation of the sense amplifier SA is controlled by a sense amplifier driving signal .phi.S. The active pull-up circuit AP comprises transistors QAP0, QR0 QAP1, and QR1, and capacitors CR0 and CR1. The transistors QAP0 and QR0, and the capacitor CR0 function to pull up the potential of the bit line BL. The transistors QAP1 and QR1, and the capacitor CR1 function to pull up the potential of the bit line XBL. More particularly, the transistor QAP0 pulls up the potential of the bit line BL, and is connected between the bit line BL and a power supply line VCC. The capacitor CR0 is used to boost the gate potential of the transistor QAP0. One end of the capacitor CR0 is connected to the gate of the transistor QAP0, and the other end thereof receives the active pull-up clock signal .phi.R. The transistor QR0 functions to charge the capacitor CR0 up to a precharge voltage of the bit line BL, and is connected between the bit line BL and the capacitor CR0. The transistors QAP1 and QR1, and the capacitor CR1 are configured in the same manner as the above. The clock signal .phi.R is applied to the gates of the transistors QR0 and QR1.
FIG. 4 is a block diagram of the active pull-up circuit driving system 20 shown in FIG. 1. The system 20 comprises a clock signal generator 30 generating the clock signal .phi.R, which is the same as the clock signal .phi.R1 used in the circuit shown in FIG. 2. The clock signal .phi.R generated by the generator 30 is applied, as the clock signal .phi.R, to the memory cell block MA1, and is applied to a delay circuit D11. The delay circuit D11 delays the clock signal .phi.R, and outputs, as the clock signal .phi.R2, a delayed clock signal to the memory cell block MA2. The above delayed clock signal is applied to a delay circuit D12, which delays it by a delay time identical to that of the delay circuit D11. A delayed clock signal generated by the delay circuit D12 is output, as the clock signal .phi.R3, to the memory cell block MA3, and is applied to a delay circuit D13. The delay circuit D13 has the same delay time as the delay time of each of the delay circuits D11 and D12, and delays the delayed clock signal from the delay circuit D12. A delayed clock signal generated by the delay circuit D13 is output, as the clock signal .phi.R, to the memory cell block MA4.
As shown in FIG. 5, the clock signals .phi.R1-.phi.R4 are generated, in that order, at different times. The pull-up operations of the memory cell blocks MA1-MA4 are respectively controlled by the clock signals .phi.R1-.phi.R4, and are activated at the different times. In this case, the instantaneous current can be greatly decreased, as compared with the case where the pull-up operations of the memory cell blocks MA1-MA4 are concurrently started. Hence, the load applied to the power supply can be reduced, and a small-scale power supply can be used.
FIG. 6 shows another control method similar to the method shown in FIGS. 4 and 5. A sense amplifier activating signal .phi.LE is applied to a sense amplifier in one of a plurality of memory cell blocks. As shown in FIG. 12B, sense amplifier activating signals .phi.LE11, .phi.LE12, .phi.LE13 and .phi.LE14 are respectively applied to four memory cell blocks at different times in order to reduce the instantaneous current. That is, the instantaneous current flowing in the memory when the sense amplifiers in one of the four memories start to operate is less than the instantaneous current passing in the memory when the sense amplifiers of the entire memory cell array start to operate.
However, the above-mentioned conventional methods have the following disadvantages. As is well known, parasitic capacitors are coupled to bit lines. Hence, it takes a certain time for pieces of information stored in memory cells to be read therefrom after the corresponding word line is selected and to reach the corresponding sense amplifiers. The above time is longest when the word line furthest from the alignment of the sense amplifiers is selected. Hence, it is necessary to select the operation timing of the memory cell block which starts to operate first (the operation timing at which the clock signal .phi.LE11 is activated) so that the above memory cell block starts to operate after pieces of information stored in the memory cells connected to the word line furthest from the sense amplifiers are completely read therefrom. Further, the clock signals .phi.LE12, .phi.LE13 and .phi.LE14 are activated after the clock signal .phi.LE11 is activated. Hence, it takes a long access time for all the memory cell blocks to start to operate. As a result, it is very difficult to reconcile the suppression of instantaneous current flowing when the sense amplifiers start to operate and the reduction in access time.